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? t e chnology sii 1160 panellink t ransmitter dat a sheet document # sii -ds-0126-b
sii 1 160 panellink t r ansmitter dat a sheet silicon image, inc. sii -ds-0126-b march 2005 application information t o obt ain the most updated application no tes and other useful information for your design, please visit the silicon image web site at www .siliconimage.com or cont act your local silicon image sales of fice. copy right notice this manual is copyrighted by silicon image, inc. do not reproduce, transform to any other format, or send/transmit any p a rt of this document ation without the expressed written permi ssion of silicon image, inc. t r ademark acknow ledgment silicon image, the silicon image logo, panellink ? and the panellink ? digit a l logo are registered trademarks of silicon image, inc. tmds tm is a trademark of silicon image, inc. i 2 c is a trademark of philip s semiconductor . all other trademarks are the property of their respective holders. disclaimer this document provides technical information for the user . silicon image, inc. reserves the right to modify the information in this document as necessary . the customer should make sure that they have the most recent dat a sheet version. silicon image, inc. holds no responsibility for any errors that may appear in this document. customers should t a ke appropriate action to ensure their use of the product s does not infringe upon any p a tent s. silicon image, inc. respect s valid p a tent right s of th ird p a rties and does not infringe upon or assist others to infringe upon such right s. all information cont ained herein is subject to change w i thout notice. revision history rev i s i o n d a t e c o m m e n t a 07/07/04 data sheet ? 1 st release b 03/01/05 data sheet ? 2 nd release ? added i 2 c registers and pins, added dual zone pll information, corrected recommended r ex t _ sw in g value from 380 ? to 510 ? , corrected package jedec code, added reset description. ? 2005 silicon image. inc. sii -ds-0126-b ii
sii 1 160 panellink t r ansmitter dat a sheet t able of contents general description ............................................................................................................................... ......... 1 features ............................................................................................................................... ....................... 1 functional description ............................................................................................................................... ..... 3 electrical s pecifications ............................................................................................................................... ... 4 absolute maximum conditions ................................................................................................................... 4 normal operating conditions ..................................................................................................................... 4 digit a l i/o s pecifications ............................................................................................................................. 4 dc s pecifications ............................................................................................................................... ......... 5 ac s pecifications ............................................................................................................................... ......... 5 input t i ming diagrams ............................................................................................................................... .6 pin descriptions ............................................................................................................................... ............... 8 input pins ............................................................................................................................... ..................... 8 control and configuration pins ................................................................................................................... 8 power management pins ............................................................................................................................ 9 dif f erential signal dat a pins ....................................................................................................................... 9 local control (i 2 c) interfac e ....................................................................................................................... 9 reserved pins ............................................................................................................................... ............ 10 power and ground pins ............................................................................................................................ 10 feature information ............................................................................................................................... ....... 1 1 i 2 c interfac e ............................................................................................................................... ............... 1 1 i 2 c register mapping ............................................................................................................................... .1 2 dual zone pll ............................................................................................................................... ........... 13 manual zone control ............................................................................................................................. 13 automatic zone control ......................................................................................................................... 14 reset descript i on ............................................................................................................................... ....... 14 tft panel dat a mapping .......................................................................................................................... 15 design recommendations ........................................................................................................................... 20 dif f erences between sii 160 and sii 1 160 ............................................................................................... 20 ext_swing selec t ion ............................................................................................................................. 20 pcb ground planes ............................................................................................................................... ... 20 v o lt age ripple regulation ......................................................................................................................... 20 s p read s pectrum support ......................................................................................................................... 21 res e t circ uit for i 2 c application ................................................................................................................ 22 power control ............................................................................................................................... ............ 22 decoupling cap a citors .............................................................................................................................. 2 3 series damping resistors on output s ...................................................................................................... 24 source t e rmination resist ors on dif f erential output s .............................................................................. 24 dif f erential t r ace routing ......................................................................................................................... 25 package dimensions ............................................................................................................................... ..... 28 package ............................................................................................................................... ..................... 28 ordering information ............................................................................................................................... .. 28 iii sii - ds-0126-b
sii 1 160 panellink t r ansmitter dat a sheet list of t ables t able 1. general i 2 c register bit s ................................................................................................................ 13 t able 2. dual zone pll i 2 c control register bit s ........................................................................................ 14 t able 3. one pixel/clock input/output tft mode ........................................................................................ 15 t able 4. t w o pixels/clock input/output tft mode ...................................................................................... 16 t able 5. 24-bit one pixel/clock input with 24-bit t w o pixels/clock output tft mode ................................ 17 t able 6. 18-bit one pixel/clock input with 18-bit t w o pixels/clock output tft mode ................................ 18 t able 7. t w o pixels/clock input with one pixel/clock output tft mode .................................................... 19 t able 8. new pin functions for sii 1 160 tx .................................................................................................. 20 t able 9. power consumption characteristics .............................................................................................. 22 t able 10. recommended component s for byp a ss and decoupling circuit s ............................................... 23 t able 1 1 . routing guidelines for dvi t r aces ................................................................................................ 27 list of figures figure 1. system block diagram ? t y pical application .................................................................................. 1 figure 2. pin diagram for sii 1 160 ................................................................................................................. 2 figure 3. functional block diagram ............................................................................................................... 3 figure 4. clock cycle high/low t i mes ........................................................................................................... 6 figure 5. input dat a setup/hold t i me to idck .............................................................................................. 6 figure 6. vsync, hsync and ctl[3:1] delay t i me from de ...................................................................... 6 figure 7. de high and low t i mes .................................................................................................................. 6 figure 8. reset t i ming at power-up or prior to first i 2 c a ccess ................................................................... 7 figure 9. i 2 c byte read ............................................................................................................................... .1 1 figure 10. i 2 c byte w r ite .............................................................................................................................. 1 1 figure 1 1 . v o lt age regulation using lm317emp ......................................................................................... 20 figure 12. planned s p read s pectrum support circuit ................................................................................. 21 figure 13. t y pical reset circuit .................................................................................................................... 22 figure 14. decoupling and byp a ss cap a citor placement ............................................................................ 23 figure 15. decoupling and byp a ss schematic ............................................................................................. 23 figure 16. series input dampi ng resistors for driving source ................................................................... 24 figure 17. dif f erential output source t e rminations .................................................................................... 24 figure 18. source t e rmi nation layout illustration ........................................................................................ 25 figure 19. example of incorrect dif f erential signal routing ........................................................................ 26 figure 20. example of correct dif f erential signal routing ........................................................................... 26 figure 21. dif f erential t r ace routing to dvi connector (t op side v i ew) .................................................... 26 figure 22. 100-pin tqfp package dim ensions (jedec code ms-026-aed) ............................................ 28 sii -ds-0126-b iv
sii 1 160 panellink t r ansmitter dat a sheet general description the si i 1 160 transmitter uses panellink digit a l technology to support displays up to uxga resolution. it support s up to true-color p anels (24 bit s per pixel, 16.7m colors) in 1 or 2 pixels-per-clock mode. all panellink product s are designed on scaleable cmos architecture to support future performance requirement s while maint a ining the same logical interface. the si i 1 160 transmitter follows this strategy by of fering a pin-comp atible upgrade to the si i 160 transmitter that also br ings longer cable support. panellink digit a l technology simplifies the pc & display interface by resolv ing many of the system level issues associated with high-speed digit a l design, providing the system designer with a digit a l solution that is quicker to market and lower in cost. features ? scaleable bandwidth: 25-165 mhz (vga to uxga) ? backwards compatible replacement for the sii 160 trans mitter ? high skew inter pair tolerance: 1 full input clock cycle (6ns at 165 mhz) ? flexible interface: single or dual pixel input at up to 48 bits ? cable distance support: over 20m dvi cable ? fully dvi 1.0 compliant ? advanced on-chip input clock jitter filter to ensure clean output to receiver ? available in universal package for both standard and pb-free (environmentally-friendly) applications. si i 116 0 tm ds tx ev e n pi x e l dat a odd p i xel dat a co n t ro l cl ock t m ds over d v i cab l e or fl a t c a b l e vi d e o pro ces so r si i 11 61 tm ds rx pa nel co nt r o lle r 24 / 24 / even pi xel da t a odd pi xel dat a cont rol cl ock 24 / 24 / figure 1. sy stem block diagram ? t y pical application 1 sii -ds-0126-b
sii 1 160 panellink t r ansmitter dat a sheet figure 2. pin diagram for sii 1 160 di e 1 3 1 si i 1160 1 0 0 - p i n tq fp ( top v i e w ) di e 1 2 2 di e 1 1 3 di e 1 0 4 di e 9 5 di e 8 6 gn d 7 vc c 8 di e 7 9 di e 6 10 di e 5 11 di e 4 12 di e 3 13 di e 2 14 di e 1 15 di e 0 16 iv c c 17 pv c c 1 18 pg nd 1 19 sc l 20 ms en 21 rsvd 22 sd a 23 ed ge 24 pi x s 25 pd 26 rs v d 27 rs v d 28 rs v d 29 vc c 30 gn d 31 ext _ s w i n g 32 ag n d 33 tx c - 34 tx c + 35 avc c 36 ag n d 37 rs v d 38 tx 0 - 39 tx 0 + 40 ag n d 41 tx 1 - 42 tx 1 + 43 avc c 44 tx 2 - 45 tx 2 + 46 ag n d 47 di o 2 3 48 di o 2 2 49 di o 2 1 50 75 di o1 74 di o2 73 di o3 72 di o4 71 di o5 70 di o6 69 di o7 68 gn d 67 iv cc 66 di o8 65 di o9 64 di o10 63 di o11 62 di o12 61 di o13 60 di o14 59 di o15 58 gn d 57 vc c 56 di o16 55 di o17 54 di o18 53 di o19 52 di o20 51 di o0 di e 1 4 10 0 di e 1 5 99 iv c c 98 di e 1 6 97 di e 1 7 96 di e 1 8 95 di e 1 9 94 di e 2 0 93 di e 2 1 92 di e 2 2 91 di e 2 3 90 gn d 89 vc c 88 is e l /r s t 87 p g nd2 86 p v cc2 85 ct l 1 84 ct l 2 83 ct l 3 82 iv c c 81 i dck 80 gn d 79 de 78 v syn c 77 h syn c 76 d i ff er en tia l s i gn als od d 8 - b i t s r e d eve n 8-b i ts red o dd 8 - b i t s g r e e n ev en 8 - b i t s g r een o dd 8 - b i t s bl ue e v e n 8 - b i t s bl ue c o nf i g u rat i o n p i ns pl l pll c o ntro ls in p u t cl o c k gp i co nt ro l sii -ds-0126-b 2
sii 1 160 panellink t r ansmitter dat a sheet 3 sii -ds-0126-b functional description the sii 1 160 tx is a dvi 1.0 compliant panellink transmitter in a comp act p a ckage. it provides 48 bit s for dat a input to allow for p anel support up to uxga. fi gure 3 shows the functional blocks of the chip. da ta ca ptu r e l ogic de hsync vsync c tl3 c tl2 c tl1 idck ext_ s wi ng tx 0 dat a dat a 24 die[ 2 3 : 0 ] dio[ 23 : 0 ] en co der 0 hsync vsync en co der 1 en co der 2 ct l 1 dat a ct l2 ct l3 24 ji tter fil t e r ma i n pll swin g co ntr o l tx 1 tx 2 txc tx 0 + tx 0 - tx 1 + tx 1 - tx 2 + tx 2 - tx c + tx c - sda scl edg e pi xs i 2 c r e giste r s ---- ------- c o nf i g u r at i o n log ic ---- ------- me s s a g e e n co de r lo gi c ct l0 c onf i g in f o figure 3. functional block diagram
sii 1 160 panellink t r ansmitter dat a sheet sii -ds-0126-b 4 electrical s p ecifications absolute maximum conditions sy mbol parameter min ty p max unit s v cc 1 supply voltage 3.3v -0.3 4.0 v v i input voltage -0.3 v cc + 0.3 v v o 2 input voltage -0.3 v cc + 0.3 v t j junction t e mperature (w it h pow er applied) 125 c t st g storage t e mperature -65 150 c note 1. permanent device damage may occur if abs olute maximum conditions are exceeded. 2. f unctional operation should be restricted to the c onditions described under normal operating conditions. normal operating conditions sy mbol parameter min ty p max unit s v cc supply voltage 3.0 3.3 3.6 v v ccn supply voltage noise 100 mv p- p t a ambient t e mperature (w it h pow er applied) 0 25 70 c ja t hermal resistance (junction to ambient) 1 5 3 c/w note 1. airflow at 0m/s. digital i/o specifications under normal operating conditions unless otherwise specified. sy mbol parameter conditions min ty p max unit s v ih high-level input voltage 2 v v il low -level input voltage 0.8 v v oh high-level input voltage 2.4 v v ol low -level input voltage 0.4 v v cinl input clamp voltage 1 i cl = -18ma gnd -0.8 v v cip l input clamp voltage 1 i cl = 18ma ivcc + 0.8 v v conl input clamp voltage 1 i cl = -18ma gnd -0.8 v v cop l input clamp voltage 1 i cl = 18ma ovcc + 0.8 v i ol input leakage current high impedance -10 10 a note 1. guaranteed by design. volt age undershoot or overshoot c annot exceed absolute maximum conditions for a pulse of greater than 3 ns or one th ird of the clock cy cle.
sii 1 160 panellink t r ansmitter dat a sheet 5 sii -ds-0126-b dc specifications under normal operating conditions, with r ext _sw ing = 510 ? and using source termination, unless otherwise specified. sy mbol parameter conditions min ty p max unit s v od differential voltage single ended peak to peak amplitude r load = 5 0 ? 510 550 590 mv v doh differential high-level output voltage 1 a v c c v i dos differential output short circuit current 1 v out = 0 v 5 a i pd pow e r-dow n current 2 5 m a i cct t r ansmitter supply current idck= 165 mhz, tw o pixel per clock mode ivcc = vcc, worst case pattern 3 140 200 ma notes 1. guaranteed by design. 2. assumes all inputs to the transmitter are not toggling. 3. t he w o rst case pattern consists of a black and w h ite checkerboard pattern, each checker one pixel w i de. ac specifications under normal operating conditions with source termination and the recommended r ext _sw i ng value unless otherwise specified. sy mbol parameter conditions min max unit s t cip idck period, 1 pixel/clock 6 40 ns f cip idck f r equency , 1 pixel/clock 25 165 mhz t cip idck period, 2 pixels/clock 12 80 ns f cip idck f r equency , 2 pixels/clock 12 81 mhz t cih idck high t i me at 165mhz 2 ns t cil idck low t i me at 165mhz 2 ns t sid f data, de, vsync, hsync, and ct l[3:1] setup t i me to idck falling edge edge = 0 1.5 n s t hidf data, de, vsync, hsync, and ct l[3:1] hold t i me from idck falling edge edge = 0 1.5 ns t sid r data, de, vsync, hsync, and ct l[3:1] setup t i me to idck rising edge edge = 1 1.5 ns t hidr data, de, vsync, hsync, and ct l[3:1] hold t i me from idck rising edge edge = 1 1.5 ns t ddf vsync, hsync, and ct l[3:1] delay from de falling edge 1 t cip n s t ddr vsync, hsync, and ct l[3:1] delay to de rising edge 1 t cip n s t hde de high time 1 8191t cip ns t ld e de low time 1 1 2 8 t cip n s t i2 cdv d sda data valid delay from scl high to low transition c l = 400pf 1000 ns t r eset isel/rst signal high t i me required for valid i 2 c reset 50 s notes 1. guaranteed by design. 2. all t m ds signaling is guaranteed to meet the dvi 1.0 specifications. 3. all standard mode i 2 c (100khz and 400khz) timing require ments are guaranteed by design.
sii 1 160 panellink t r ansmitter dat a sheet sii -ds-0126-b 6 input timing diagrams t cih t cil t cip 80% vcc 20% vcc 20% vcc 80% vcc 80% vcc figure 4. clock cy cle high/low t i mes d[23:0], de, hsync,vsync idck t sidf t hidf t sidr t hidr 50 % 50 % 50 % 50 % figure 5. input dat a setup/hold t i me to idck t dd r t dd f de vs yn c , h s yn c , c t l [ 3: 1] 20% v c c 20% v c c 20 % v c c 20% v c c de vs yn c , h s y n c , c t l [ 3: 1] figure 6. vsync, hsync and ctl[3:1] delay t i me from de de t lde t hde 20% vcc 80% vcc 20% vcc 80% vcc figure 7. de high and low t i mes
sii 1 160 panellink t r ansmitter dat a sheet 7 sii -ds-0126-b v cc ma x t res e t v cc mi n v cc isel/r st t r ese t figure 8. reset t i ming at pow e r-up or prior to first i 2 c access
sii 1 160 panellink t r ansmitter dat a sheet sii -ds-0126-b 8 pin descriptions input pins pin name pin # ty pe descrip tio n die23- die0 see sii 1160 pin diagram in input even data[23:0] corresponds to 24-bit pixel data for 1-pixel/clock input mode and to the first 24-bit pixel data for 2-pixels/clock mode. input data is sy nchronized w i th input data clock (idck). data can be latched on the rising of t he falling edge of idck depending on w hether edge is high or low , respectively . refer to t f t panel data mapping in this document and dst n panel data mapping application note ( sii -an-0007-a), w h ich tabulates the re lationship betw een the input data to the transmitter and output data from the receiver dio23- dio0 see sii 1160 pin diagram in input odd data[23:0] corre sponds to the second 24-bit pixe l data for 2-pixels/clock mode. t i e all pins to low w hen not in use. input data is sy nchronized w i th input data clock (idck). data can be latched on the rising of t he falling edge of idck depending on w hether edge is high or low , respectively . dual link is not supported. idck 80 in input data clock. i nput data and control signals can be va lid either on the falling or the rising edge of idck as selected by the edge pin. de 78 in input data enable. t h is signal qualifies t he active data area. de is alw a y s required by the transmitter and must be high during active display time and low during blanking time. hsync vsync 76 77 in in horizontal sy nc input control signal. vertical sy nc input control signal. control and configuration pins pin name pin # ty pe descrip tio n edge 24 in data/control latching edge. a low leve l indicates that all i nput signals(die/dio[23:0], hsync, vsync, de and ct l[3: 1] are latched on the falling edge of idck, w h ile a high level(3.3v) indicates that all input signal s are latched on the rising edge of idck. w hen the i 2 c interface is enabled (isel/rst = l ow ), this pin is ignored and the edge register bit is used instead. pixs 25 in pixel select. a low level indicate s one pixel (up to 24-bits) per clock mode using die[23:0]. a high level (3.3v) indicates tw o pixels (up to 48-bits) per clock mode using die[23:0] for the first pix e l and dio[23:0] for the second pix e l. ct l 1 8 4 i n general input control signal 1. ss_clk_in spread spectrum clock input (future). a planned future variation of this device w ill allow a spread spectrum version of ss_clk_out to be driven into this pin, at w h ich time pin 29 w ill become ct l1. ct l 2 8 3 i n general input control signal 2. ss_clk_out out spread spectrum clock output (futur e). a planned future variation of this device w ill allow a clock to be driven out of this pin fo r conditioning by a spread spectrum device, at w h ich time pin 28 w ill become ct l2. ct l 3 8 2 i n general input control signal 3. r s v d 2 7 i n reserved. must be tied high for normal operation. ss_en# spread spectrum enable. a planned future variation of this device w ill use this pin to enable pins 83 and 84 to handle spread spectrum clock. low = spread spectrum f eature enabled on pins 83 and 84 high = pins 83 and 84 are ct l2 and ct l1 outputs (default)
sii 1 160 panellink t r ansmitter dat a sheet 9 sii -ds-0126-b pow e r management pins pin name pin # ty pe descrip tio n pd 26 in pow e r dow n (active low ) . a high level indicates normal operation. a low level indicates pow er dow n mode. during pow er dow n mode, all data (d ie/dio[23:0]), data enable (de), clock (idck) and control signals (h sync, vsync, ct l[3:1]), input buffers are disabled, all output buffers are tri-stated and all internal circuitry is pow ered dow n. w hen the i 2 c interface is enabled (isel/rst = l ow ), this pin is ignored and the pd register bit is used instead. t i e this pin low if not used. differential signal data pins pin name pin # ty pe descrip tio n tx 0 + tx 0 - tx 1 + tx 1 - tx 2 + tx 2 - 40 39 43 42 46 45 analog analog analog analog analog analog t m ds low voltage differential signal input data pairs. t hese pins are tri-stat ed w hen pd is asserted. tx c + tx c - 35 34 analog analog t m ds low voltage differential signal input clock pair. t hese pins are tri-stat ed w hen pd is asserted. ext _ sw ing 32 analog voltage sw ing adjust. a resistor shoul d tie this pin to avcc. t h is resistor determines the amplitude of the voltage sw i ng. a smaller resistor value sets a larger voltage sw ing and vice versa. f o r remote display applic ations w i th source termination, a 510 ? resistor is recommended (see page 24). w i thout t he source termination, use a 560 ? resistor. local control (i 2 c) interface the transmitter can operate with or without an i 2 c interface connection. refer to the feature information section for det ails on using the i 2 c registers. pin name pin # ty p e description isel/rst 8 7 i n i 2 c interface select. if low , then the i 2 c interface is active. if high, the interface is inactive and chip configuration is taken from strap and default settings. t h is pin also acts as an asy n chronous reset to the i 2 c interface controller. sw itch ing this input from high to low after a minimum t r e set high time resets the i 2 c logic. msen 21 out monitor sense. t he behavio r of this output depends on w hether the i 2 c interface is enabled or disabled. no i 2 c (isel = high) msen= h igh: a pow ered on receiver is detected at the t m ds outputs. msen= l ow : a pow ered on receiver is not detected. t h is receiver sense function can only be used in dc-coupled sy stems. i 2 c enabled (isel = low ) t he output is programmable through the i 2 c interface and can indicate the hot plug or receiver sense signal state, or c an instead generate a status change interrupt for those signals. t h is pin is an open collector output. an external pull-up resistor (5k ? recommended) is required on this pin if the msen signal w ill be used. otherw i se the signal should be tied low . s c l 2 0 i n i 2 c clock. w hen the i 2 c interface is enabled (isel= l ow ), this pin acts as the i 2 c clock input. t h is pin is an open collector output. it must be pulled high to vcc through a resistor; a value of 2.2k ? is recommended for i 2 c applications, 2-5k ? otherw i se. t h is pin is not 5v-tolerant. s d a 2 3 i n / o u t i 2 c data. w hen the i 2 c interface is enabled (isel= l ow ), this pin acts as the i 2 c data input and output. t h is pin is an open collect or output. it must be pulled high to vcc through a resistor; a value of 2.2k ? is recommended for i 2 c applications, 2-5k ? otherw i se. t h is pin is not 5v-tolerant.
sii 1 160 panellink t r ansmitter dat a sheet sii -ds-0126-b 10 reserved pins it is preferable to tie indicated pins high through a 2-5k ? resistor; direct connection to vcc is not recommended. pin name pin # ty pe descrip tio n r s v d 2 2 i n reserved. must be tied high for normal operation. r s v d 2 8 i n reserved. must be tied high for normal operation. r s v d 2 9 i n reserved. must be tied high for normal operation. rsvd 38 -- reserved. should be left unconnected (but can be tied to avcc for existing si i 160 designs). pow e r and ground pins pin name pin # ty pe descrip tio n v c c 8 , 3 0 , 5 6 , 8 8 pow e r digital core vcc, must be set to 3.3v. g n d 7 , 3 1 , 5 7 , 6 7 , 7 9 , 89 ground digital core gnd. i v c c 1 7 , 6 6 , 8 1 , 9 8 pow e r input v cc, must be set to 3.3v. avcc 36,44 pow e r analog vcc must be set to 3.3v. a g n d 3 3 , 3 7 , 4 1 , 4 7 gr o u n d a n a l o g g n d . pvcc1 18 pow e r primary pll analog vcc must be set to 3.3v. pvcc2 85 pow e r f ilter pll analog vcc must be set to 3.3v. pgnd1 19 ground pll analog gnd. pgnd1 should not be directly connected to pgnd2 befor e being connected to the ground plane. t hey should be connected individually to the ground plane. pgnd2 86 ground pll analog gnd. pgnd2 should not be directly connected to pgnd1 befor e being connected to the ground plane. t hey should be connected individually to the ground plane.
sii 1 160 panellink t r ansmitter dat a sheet 11 sii -ds-0126-b feature information i 2 c interface the sii 1 160 tx provides an i 2 c slave interface for more precise control of the chip features. use of this interface is optional and is selected by the isel/rst pin. if not used, the chip register settings return to a default st ate; the edge and pd features then come under the cont rol of the respective strap pins instead. the i 2 c slave st ate machine operates from an internal clock derived from the incoming scl signal. no video clock and input is required to read and write to the i 2 c registers from address 0x00 to 0x0f . these accesses can also t a ke place using only the scl clock in power down mode. the transmitter responds to the seven-bit binary i 2 c address of 0x70. a read or wr ite transaction is determined by bit 0 of the i 2 c address. setting this bit to 0 will enable a writ e transaction and setting this bit to 1 will enable a read transaction. the i 2 c read operation is shown in figure 9, and the write operation in figure 10. page mode is not supported. s a c k s a c k a c k p slave add r ess re g i s t e r address slav e address da t a stop st a r t st a r t bu s activity : m aster sda no a c k figure 9. i 2 c by te read s a c k a c k p sl ave addres s r egister addre s s d a t a stop st a r t bu s activity : m aster sda a c k figure 10. i 2 c by te w r ite
sii 1 160 panellink t r ansmitter dat a sheet sii -ds-0126-b 12 i 2 c register mapping a ddr. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 default value notes 0x0 v n d _ i d l 0 x 0 1 0x1 v n d _ i d h 0 x 0 0 0x2 d e v _ i d l 0 x 0 6 0x3 d e v _ i d h 0 x 0 0 0x4 d e v _ r e v 0 x 0 0 0x5 rsvd 4 0x6 f r q_low 0x19 0x7 frq_high 0x64 0x8 rsvd w r ite to 00 ven hen rsvd w r ite to 01 e d g e p d 0 0 1 1 0 1 0 0 3 , 5 , 6 0x9 rsvd rsen rsvd read only 0xa rsvd w r ite to 1000000 ct l 0 1 0 0 0 0 0 0 1 5 , 6 0xb- 0xd rsvd 4 0xe rsvd w r ite to 00 e z o n e z o n e f z o n e o r s v d w r ite to 001 0 0 0 0 0 0 0 1 0xf rsvd 4 notes: 1. hexadecimal values use a prefix of ?0x?. all values use bit 7 as most significant, bit 0 as least significant. 2. read-only or read/w r ite capab ilities are noted on the next page. 3. on any reset assertion event, register s that have default values lose their pr eviously programmed value and are set back to the default values listed. 4. registers listed as rsvd and shaded gray are reserved for factor y use and should not be accessed. 5. w r ite rsvd bit s to the values indicat ed when writing other bit s in the register . 6. w r ite pd to 1 for normal operation; write ctl0 to 0 for hdmi applications.
sii 1 160 panellink t r ansmitter dat a sheet 13 sii -ds-0126-b t a ble 1. general i 2 c register bit s reg i ster name a ccess descrip tio n vnd_idl ro vendor id low by te (0x01) vnd_idh ro vendor id high by te (0x00) dev_idl ro device id low by te (0x 06) dev_idh ro device id high by te (0x00) dev_rev ro device revision (0x 00) frq_ low ro idck. low frequency limit is 25mhz. (0x19) frq_high ro idck high frequency limit is 165mhz. va lue is offset over 65mhz. (0x64) hen rw horizontal sy nc enable 0 ? hsync input is transmitted as fixed low 1 ? hsync input is transmitted as input. default ven rw vertical sy nc enable 0 ? vsync input is transmitted as fixed low 1 ? vsync input is transmitted as input. default edge rw edge select (same function as edge pin) 0 ? input data low order bits latched first default 1 ? input data high order bits latched first pd rw pow e r dow n mode (same function as pd# pin) 0 ? pow e r dow n . default after reset 1 ? normal operation rsen ro receiver sense. t h is bit is high if a pow ered on receiver is connected to the transmitter outputs, low otherw i se. t h is function is only available fo r use in dc-coupled sy stems. ctl0 rw control 0. ct l0, ct l1, ct l2, ct l3 are s ent over t m ds interface w hen de is low . ct l1-3 are driven in from external pins, but ct l0 is not available ex ternally and therefore must be set through this register. set to 0 for hdmi applications. 0 ? t r ansmit ct l0 as low 1 ? t r ansmit ct l0 as high note that w hen not in i 2 c mode, ct l0 is alw a y s transmitted as high. notes: 1. ro = read only registers 2. rw = read/w r ite registers 3. ?default? indicates value set a fter a reset event. not all bits def ault to a defined state after reset. dual zone pll the sii 1 160 tx of fers a dual-zone pll that changes it s operational p a rameters depending on the frequency zone selected. in the low zone, operation is ideal in the low frequency range, from 20mhz to around 120mhz. high zone operation is optimized in the high frequency range, above 100mhz. in the overlapping range, either low zone or high zone operation can be used. operating zone optimization contribut es to robust operation over long c ables. for example, optimized pll characteristics account for the ability of the tr ansmitter to send video at uxga over 20m cables. pll zone selection is controlled either manually or autom atically . manual zone control is the preferred mode of operation. manual zone control whenever the application allows it, pll zone selection should be made manually . the i 2 c register bit s zonef and ezone allow the host graphics controller to set t he optimal zone for the current video resolution being transmitted. for frequencies over 100mhz, the controlle r should select high zone pll operation. t able 2 describes the relevant register bit s .
sii 1 160 panellink t r ansmitter dat a sheet sii -ds-0126-b 14 automatic zone control for applications that are not able to program the i 2 c registers, the chip incorpor ates an automatic zone control circuit. this circuit determines whether the input pixe l clock is operating in the low frequency range or the high frequency range, and set s the pll zone selection accordingly . the chip default s to the automatic mode of zone select ion af t e r reset . the zone determination depends primarily on input frequency , but is also af fected by operating volt age and chip temperature. therefore, it is possi ble for an automatic zone switch to occu r while video input is st able, causing moment ary (~1 s) unevenness in the video output clock and dat a stream s. this could occur , for example, while the chip is still warming up to it s normal operating temperatur e. however , the automatic selection circuit provides wide hysteresis to ensure that there will not be any oscillation around the zone switch point. t a ble 2. dual zone pll i 2 c control register bit s reg i ster name a ccess descrip tio n zonef rw z one f o rce. enable external selection of main pll operating zone. w hen z o nef = 1, the main pll zone is selected by ez one. 0 ? automatic zone selection ? ez one bit disabled (default) 1 ? manual zone selection ? ez one bit enabled ezone rw external z one select. selects operati ng zone of main pll, but only w hen z o nef = 1 (disabled by default). 0 ? low zone (recommended for 20-120mhz) 1 ? high zone (recommended for > 100mhz) zoneo ro z one output ? indicate s current operating zone. w hen z o nef = 0 (automatic), z o neo indicates t hat pll is operating in zone optimized for: 0 = low er frequencies 1 = higher frequencies. w hen z o nef = 1 (manual), z o neo information is not used. reset description the input pin isel/rst serves as an asynchronous reset for the i 2 c slave controller in i 2 c mode. the programming registers, which are accessible over the i 2 c bus, lose their previously programmed values as soon as isel/rst is switched from high to low . i 2 c registers whose default values are not correct for normal operation must then be manually set to their appropriate value. isel/rst serves only to set the registers to their defaul t values, and to restore the interface to a known initial st ate. without an initial reset, the i 2 c interface may not respond properly . the minimum isel/rst high time for proper reset, af ter nominal vcc values have been reached, is t reset . register bit function pd is disabled af ter reset to elim inate any unexpected chip output before initialization. the st ate of this bit is set during the reset period according to the following rule: af ter a reset, the chip is turned of f; the power down control bit, pd, is forced to 0. when the chip comes out of reset (isel/rst goes low), the tmds output s will be disabled and the transmitter will be turned of f. t o turn the transmitter back on, the pd bit must be set to 1 over the i 2 c bus.
sii 1 160 panellink t r ansmitter dat a sheet 15 sii -ds-0126-b tft panel data mapping the following tft dat a mapping t ables are strictly listed for single link tft applications only . for dstn mapping please refer to application note sii -an-0007-a. sii 1 151 and sii 1 161 have the same pinout. t a ble 3. one pixel/clock input/output tft mode tft vga output tx input dat a rx output dat a tft panel input 24-bpp 18-bpp 1 160 164 1 161 141b 24-bpp 18-bpp b 0 d i e 0 d 0 q e 0 q 0 b 0 b 1 d i e 1 d 1 q e 1 q 1 b 1 b 2 b 0 d i e 2 d 2 q e 2 q 2 b 2 b 0 b 3 b 1 d i e 3 d 3 q e 3 q 3 b 3 b 1 b 4 b 2 d i e 4 d 4 q e 4 q 4 b 4 b 2 b 5 b 3 d i e 5 d 5 q e 5 q 5 b 5 b 3 b 6 b 4 d i e 6 d 6 q e 6 q 6 b 6 b 4 b 7 b 5 d i e 7 d 7 q e 7 q 7 b 7 b 5 g 0 d i e 8 d 8 q e 8 q 8 g 0 g 1 d i e 9 d 9 q e 9 q 9 g 1 g 2 g 0 d i e 1 0 d 1 0 q e 1 0 q 1 0 g 2 g 0 g 3 g 1 d i e 1 1 d 1 1 q e 1 1 q 1 1 g 3 g 1 g 4 g 2 d i e 1 2 d 1 2 q e 1 2 q 1 2 g 4 g 2 g 5 g 3 d i e 1 3 d 1 3 q e 1 3 q 1 3 g 5 g 3 g 6 g 4 d i e 1 4 d 1 4 q e 1 4 q 1 4 g 6 g 4 g 7 g 5 d i e 1 5 d 1 5 q e 1 5 q 1 5 g 7 g 5 r 0 d i e 1 6 d 1 6 q e 1 6 q 1 6 r 0 r 1 d i e 1 7 d 1 7 q e 1 7 q 1 7 r 1 r 2 r 0 d i e 1 8 d 1 8 q e 1 8 q 1 8 r 2 r 0 r 3 r 1 d i e 1 9 d 1 9 q e 1 9 q 1 9 r 3 r 1 r 4 r 2 d i e 2 0 d 2 0 q e 2 0 q 2 0 r 4 r 2 r 5 r 3 d i e 2 1 d 2 1 q e 2 1 q 2 1 r 5 r 3 r 6 r 4 d i e 2 2 d 2 2 q e 2 2 q 2 2 r 6 r 4 r 7 r 5 d i e 2 3 d 2 3 q e 2 3 q 2 3 r 7 r 5 shift clk shift clk idck idck odck odck shift clk s hift clk v s y n c v s y n c vsync vsync vsync vsync v s y n c v s y n c h s y n c h s y n c hsync h sync h sync h sync h s y n c h s y n c d e d e d e d e d e d e d e d e for 18-bit mode, the flat panel graphics controller interfaces to the transmitte r exactly the same as in the 24-bit mode; however , 6 bit s per channel (color) are used inst ead of 8. it is recommended that unused dat a bit s be tied low . as can be seen from the above t able, the dat a m apping for less than 24-bit per pixel interfaces are msb justified. the dat a is sent during active display time while the control signals are sent during blank time. note that the three dat a channels (ch0, ch1, ch2) are mapped to blue, green and red dat a respectively .
sii 1 160 panellink t r ansmitter dat a sheet sii -ds-0126-b 16 t a ble 4. t w o pixels/clock input/output tft mode tft vga output tx input dat a rx output dat a tft panel input 24-bpp 18-bpp 1 160 1 161 24-bpp 18-bpp b0 - 0 die0 qe0 b0 - 0 b1 - 0 die1 qe1 b1 - 0 b2 - 0 b0 - 0 die2 qe2 b2 - 0 b0 - 0 b3 - 0 b1 - 0 die3 qe3 b3 - 0 b1 - 0 b4 - 0 b2 - 0 die4 qe4 b4 - 0 b2 - 0 b5 - 0 b3 - 0 die5 qe5 b5 - 0 b3 - 0 b6 - 0 b4 - 0 die6 qe6 b6 - 0 b4 - 0 b7 - 0 b5 - 0 die7 qe7 b7 - 0 b5 - 0 g0 - 0 die8 qe8 g0 - 0 g1 - 0 die9 qe9 g1 - 0 g2 - 0 g0 - 0 die10 qe10 g2 - 0 g0 - 0 g3 - 0 g1 - 0 die11 qe11 g3 - 0 g1 - 0 g4 - 0 g2 - 0 die12 qe12 g4 - 0 g2 - 0 g5 - 0 g3 - 0 die13 qe13 g5 - 0 g3 - 0 g6 - 0 g4 - 0 die14 qe14 g6 - 0 g4 - 0 g7 - 0 g5 - 0 die15 qe15 g7 - 0 g5 - 0 r0 - 0 die16 qe16 r0 - 0 r1 - 0 die17 qe17 r1 - 0 r2 - 0 r0 - 0 die18 qe18 r2 - 0 r0 - 0 r3 - 0 r1 - 0 die19 qe19 r3 - 0 r1 - 0 r4 - 0 r2 - 0 die20 qe20 r4 - 0 r2 - 0 r5 - 0 r3 - 0 die21 qe21 r5 - 0 r3 - 0 r6 - 0 r4 - 0 die22 qe22 r6 - 0 r4 - 0 r7 - 0 r5 - 0 die23 qe23 r7 - 0 r5 - 0 b0 - 1 dio0 qo0 b0 - 1 b1 - 1 dio1 qo1 b1 - 1 b2 - 1 b0 - 1 dio2 qo2 b2 - 1 b0 - 1 b3 - 1 b1 - 1 dio3 qo3 b3 - 1 b1 - 1 b4 - 1 b2 - 1 dio4 qo4 b4 - 1 b2 - 1 b5 - 1 b3 - 1 dio5 qo5 b5 - 1 b3 - 1 b6 - 1 b4 - 1 dio6 qo6 b6 - 1 b4 - 1 b7 - 1 b5 - 1 dio7 qo7 b7 - 1 b5 - 1 g0 - 1 dio8 qo8 g0 - 1 g1 - 1 dio9 qo9 g1 - 1 g2 - 1 g0 - 1 dio10 qo10 g2 - 1 g0 - 1 g3 - 1 g1 - 1 dio11 qo11 g3 - 1 g1 - 1 g4 - 1 g2 - 1 dio12 qo12 g4 - 1 g2 - 1 g5 - 1 g3 - 1 dio13 qo13 g5 - 1 g3 - 1 g6 - 1 g4 - 1 dio14 qo14 g6 - 1 g4 - 1 g7 - 1 g5 - 1 dio15 qo15 g7 - 1 g5 - 1 r0 - 1 dio16 qo16 r0 - 1 r1 - 1 dio17 qo17 r1 - 1 r2 - 1 r0 - 1 dio18 qo18 r2 - 1 r0 - 1 r3 - 1 r1 - 1 dio19 qo19 r3 - 1 r1 - 1 r4 - 1 r2 - 1 dio20 qo20 r4 - 1 r2 - 1 r5 - 1 r3 - 1 dio21 qo21 r5 - 1 r3 - 1 r6 - 1 r4 - 1 dio22 qo22 r6 - 1 r4 - 1 r7 - 1 r5 - 1 dio23 qo23 r7 - 1 r5 - 1 s h i f t c l k / 2 s h i f t c l k / 2 idck odck shift clk shift clk v s y n c v s y n c v s y n c v s y n c v s y n c v s y n c h s y n c h s y n c h s y n c h s y n c h s y n c h s y n c d e d e d e d e d e d e
sii 1 160 panellink t r ansmitter dat a sheet 17 sii -ds-0126-b t a ble 5. 24-bit one pixel/clock input w i th 24-bit t w o pixels/clock output tft mode tft vga output tx input dat a rx output dat a tft panel input 24-bpp 1 160 164 1 161 24-bpp b0 die0 d0 qe0 b0 - 0 b1 die1 d1 qe1 b1 - 0 b2 die2 d2 qe2 b2 - 0 b3 die3 d3 qe3 b3 - 0 b4 die4 d4 qe4 b4 - 0 b5 die5 d5 qe5 b5 - 0 b6 die6 d6 qe6 b6 - 0 b7 die7 d7 qe7 b7 - 0 g0 die8 d8 qe8 g0 - 0 g1 die9 d9 qe9 g1 - 0 g2 die10 d10 qe10 g2 - 0 g3 die11 d11 qe11 g3 - 0 g4 die12 d12 qe12 g4 - 0 g5 die13 d13 qe13 g5 - 0 g6 die14 d14 qe14 g6 - 0 g7 die15 d15 qe15 g7 - 0 r0 die16 d16 qe16 r0 - 0 r1 die17 d17 qe17 r1 - 0 r2 die18 d18 qe18 r2 - 0 r3 die19 d19 qe19 r3 - 0 r4 die20 d20 qe20 r4 - 0 r5 die21 d21 qe21 r5 - 0 r6 die22 d22 qe22 r6 - 0 r7 die23 d23 qe23 r7 - 0 qo0 b0 - 1 qo1 b1 - 1 qo2 b2 - 1 qo3 b3 - 1 qo4 b4 - 1 qo5 b5 - 1 qo6 b6 - 1 qo7 b7 - 1 qo8 g0 - 1 qo9 g1 - 1 qo10 g2 - 1 qo11 g3 - 1 qo12 g4 - 1 qo13 g5 - 1 qo14 g6 - 1 qo15 g7 - 1 qo16 r0 - 1 qo17 r1 - 1 qo18 r2 - 1 qo19 r3 - 1 qo20 r4 - 1 qo21 r5 - 1 qo22 r6 - 1 qo23 r7 - 1 shift clk idck idck odck shift clk/2 v s y n c v s y n c v s y n c v s y n c v s y n c h s y n c h s y n c h s y n c h s y n c h s y n c d e d e d e d e d e
sii 1 160 panellink t r ansmitter dat a sheet sii -ds-0126-b 18 t a ble 6. 18-bit one pixel/clock input w i th 18-bit t w o pixels/clock output tft mode tft vga output tx input dat a tx output dat a tft panel input 18-bpp 1 160 164 1 161 141b 18-bpp d i e 0 d 0 q e 0 d i e 1 d 1 q e 1 b0 die2 d2 qe2 q0 b0 - 0 b1 die3 d3 qe3 q1 b1 - 0 b2 die4 d4 qe4 q2 b2 - 0 b3 die5 d5 qe5 q3 b3 - 0 b4 die6 d6 qe6 q4 b4 - 0 b5 die7 d7 qe7 q5 b5 - 0 d i e 8 d 8 q e 8 d i e 9 d 9 q e 9 g0 die10 d10 qe10 q6 g0 - 0 g1 die11 d11 qe11 q7 g1 - 0 g2 die12 d12 qe12 q8 g2 - 0 g3 die13 d13 qe13 q9 g3 - 0 g4 die14 d14 qe14 q10 g4 - 0 g5 die15 d15 qe15 q11 g5 - 0 d i e 1 6 d 1 6 q e 1 6 d i e 1 7 d 1 7 q e 1 7 r0 die18 d18 qe18 q12 r0 - 0 r1 die19 d19 qe19 q13 r1 - 0 r2 die20 d20 qe20 q14 r2 - 0 r3 die21 d21 qe21 q15 r3 - 0 r4 die22 d22 qe22 q16 r4 - 0 r5 die23 d23 qe23 q17 r5 - 0 q o 0 q o 1 qo2 q18 b0 - 1 qo3 q19 b1 - 1 qo4 q20 b2 - 1 qo5 q21 b3 - 1 qo6 q22 b4 - 1 qo7 q23 b5 - 1 q o 8 q o 9 qo10 q24 g0 - 1 qo11 q25 g1 - 1 qo12 q26 g2 - 1 qo13 q27 g3 - 1 qo14 q28 g4 - 1 qo15 q29 g5 - 1 q o 1 6 q o 1 7 qo18 q30 r0 - 1 qo19 q31 r1 - 1 qo20 q32 r2 - 1 qo21 q33 r3 - 1 qo22 q34 r4 - 1 qo23 q35 r5 - 1 shift clk idck idck odck shift clk/2 shift clk/2 v s y n c v s y n c v s y n c v s y n c v s y n c v s y n c h s y n c h s y n c h s y n c h s y n c h s y n c h s y n c d e d e d e d e d e d e
sii 1 160 panellink t r ansmitter dat a sheet 19 sii -ds-0126-b t a ble 7. t w o pixels/clock input w i th one pixel/clock output tft mode tft vga output tx input dat a rx output dat a tft panel input 24-bpp 18-bpp 1 160 1 161 141b 24-bpp 18-bpp b0 - 0 die0 qe0 q0 b0 b1 - 0 die1 qe1 q1 b1 b2 - 0 b0 - 0 die2 qe2 q2 b2 b0 b3 - 0 b1 - 0 die3 qe3 q3 b3 b1 b4 - 0 b2 - 0 die4 qe4 q4 b4 b2 b5 - 0 b3 - 0 die5 qe5 q5 b5 b3 b6 - 0 b4 - 0 die6 qe6 q6 b6 b4 b7 - 0 b5 - 0 die7 qe7 q7 b7 b5 g0 - 0 die8 qe8 q8 g0 g1 - 0 die9 qe9 q9 g1 g2 - 0 g0 - 0 die10 qe10 q10 g2 g0 g3 - 0 g1 - 0 die11 qe11 q11 g3 g1 g4 - 0 g2 - 0 die12 qe12 q12 g4 g2 g5 - 0 g3 - 0 die13 qe13 q13 g5 g3 g6 - 0 g4 - 0 die14 qe14 q14 g6 g4 g7 - 0 g5 - 0 die15 qe15 q15 g7 g5 r0 - 0 die16 qe16 q16 r0 r1 - 0 die17 qe17 q17 r1 r2 - 0 r0 - 0 die18 qe18 q18 r2 r0 r3 - 0 r1 - 0 die19 qe19 q19 r3 r1 r4 - 0 r2 - 0 die20 qe20 q20 r4 r2 r5 - 0 r3 - 0 die21 qe21 q21 r5 r3 r6 - 0 r4 - 0 die22 qe22 q22 r6 r4 r7 - 0 r5 - 0 die23 qe23 q23 r7 r5 b0 - 1 dio0 b1 - 1 dio1 b2 - 1 b0 - 1 dio2 b3 - 1 b1 - 1 dio3 b4 - 1 b2 - 1 dio4 b5 - 1 b3 - 1 dio5 b6 - 1 b4 - 1 dio6 b7 - 1 b5 - 1 dio7 g0 - 1 dio8 g1 - 1 dio9 g2 - 1 g0 - 1 dio10 g3 - 1 g1 - 1 dio11 g4 - 1 g2 - 1 dio12 g5 - 1 g3 - 1 dio13 g6 - 1 g4 - 1 dio14 g7 - 1 g5 - 1 dio15 r0 - 1 dio16 r1 - 1 dio17 r2 - 1 r0 - 1 dio18 r3 - 1 r1 - 1 dio19 r4 - 1 r2 - 1 dio20 r5 - 1 r3 - 1 dio21 r6 - 1 r4 - 1 dio22 r7 - 1 r5 - 1 dio23 s h i f t c l k / 2 s h i f t c l k / 2 i d c k o d c k o d c k s h i f t c l k s h i f t c l k v s y n c v s y n c v s y n c v s y n c v s y n c v s y n c v s y n c h s y n c h s y n c h s y n c h s y n c h s y n c h s y n c h s y n c d e d e d e d e d e d e d e
sii 1 160 panellink t r ansmitter dat a sheet sii -ds-0126-b 20 design recommendations differences betw een sii 160 and sii 1160 the sii 1 160 tx is a pin-comp atible upgrade to the sii 160 tx. it provides improved cable length support without any changes to the pinout. interrupt cap ability is al so a new option using the optional msen pin. the sii 1 160 tx can also act as to repeat hdmi signals when it s internal registers are programmed appropriately; this application requires the use of an i 2 c interface, optionally available on the sda and scl pins. t a ble 8. new pin functions for sii 1 160 tx pin sii 160 sii 1160 20 rsvd ? t i ed high optional i 2 c interface pin scl 21 rsvd ? t i ed low optional interrupt output msen 23 rsvd ? t i ed high optional i 2 c interface pin sda 87 rsvd ? t i ed high isel/rst ext_swing selection the recommended r ext _sw i ng resistor value for the ext_swing pin is provided in the pin descriptions section. this value can be adjusted as needed to optimize the dvi signal swing levels according to the needs of the application. this adjustment might become necessa ry , for example, when deviating from the recommended source termination values (described in the source t e rmination resistors on dif f er ential output s section) to optimize for a specific cabling environment. pcb ground planes all ground pins on the device should be connected to the same, contiguous ground plane in the pcb. this help s to avoid ground loop s and induct ances from one ground plane segment to another . such low-induct ance ground p a ths are critical for return current s, which af fe ct emi performance. the entire ground plane surrounding the panellink transmitter should be one piece, and in clude the ground vias for the dvi connector . voltage ripple regulation the power supply to pvcc is very import ant to the pr oper operation of the t r ansmitter chip s. pvcc does not draw much current so any volt age regulator that can s upply 50ma or more is suf f icient. a suggested regulator circuit using a low-dropout regulator is shown in figure 1 1 . note that alter native volt age regulator circuit s should be considered only if they meet the lm317 st andards of line/load regulation. decoupling and byp a ss cap a citors are also involved with power supply connections, as described in det ail in figure 14 and figure 15. 240 ? 1% 390 ? 1% vin 12v vout 3.3v adj v i n v out lm 317e mp figure 1 1 . v o lt age regulation using lm317emp
sii 1 160 panellink t r ansmitter dat a sheet 21 sii -ds-0126-b spread spectrum support tmds architecture is inherently jitter-tolerant. s p read spectrum clocking can be applied to the clock and p a rallel dat a input s of the sii 1 160 to allow for reduced emi. the spread will be prop agated throughout the system due to tmds clock architecture, which p a sses nearly all low-frequency component s of the incoming clock without attenuation. the amount of spread that can be app lied without af fecting the dvi eye is limited to 0.5% with the current p a rt, depending on the spreading algorithm empl oyed by the external spread spectrum device. a planned future variation of this chip will allow it s inte rnal clock to be coupled directly to a spread spectrum device. the expected result will be the ability to accomm odate larger amount s of spread, and it will also work in 48-bit mode as well as 24-bit mode. designs should ma ke accommodations using pins 27, 83, and 84 as noted in the pin descriptions section so that the pl anned p a rt can become a drop-in replacement for the sii 1 160. figure 12 illustrates how a design can anticip ate the ex pected future chip version. cont act phaselink corporation for additional informati on on their spread spectrum device. 1-f i n phaselink pll7 01 -21 2-s 2 3-s 1 4-s 0 vdd- 8 s3 - 7 gnd- 5 fo ut- 6 83 - s s_ c l k _ o u t si i 1160 / or future ss versi o n 84 - s s_ c l k _ i n 27- ss_ en# 3.3v 3.3v 3.3v 1160: s t uff ss : s t uff 1160: n o s t uff s s : s t uff 0 ? figure 12. planned s p read s p ectrum support circuit
sii 1 160 panellink t r ansmitter dat a sheet sii -ds-0126-b 22 reset circuit for i 2 c application if the design uses the i 2 c interface to control the transmitter features, it must also provide a means of toggling the isel/rst pin to achieve the correct t reset timing. if a local microcontroller is hosting the i 2 c connection, the easiest way to provide the reset is to connect a gpio pin from the microc ontroller to the transmitter chip as shown in figure 13. the reset pulse can then be commanded eit her at power-up time or just prior to initial use of the i 2 c interface as shown in figure 8. si i 1160 sc l sd a ise l /rs t uc figure 13. t y pical reset circuit pow e r control the low-power st andby st ate feature of the chip provides a design option of leavi ng the chip always powered, as opposed to powering it on and of f. leaving the chip powered and using the pd pin to put it in a lower power st ate may result in faster system response time , depending on the system vcc supply ramp-up delay . t able 9 provides information on chip functional mode current requirement s. these val ues are not specifications, but are represent ative of typical chip power consumpt ion. pvcc1 and pvcc2 are the power planes that are most sensitive to excessive noise. noise on these pl anes can be more easily controlled when they are regulated separately from digital vcc. t a ble 9. pow e r consumption characteristics sy mbol parameter conditions ty p unit s i cct t o tal t r ansmitter operating current see spec. i avc c current on avcc 165mhz 17-19 % of total i cct i p v cc1 current on pvcc1 31-33 % of total i cct i p v cc2 current on pvcc2 10-11 % of total i cct i vc c + i ivc c current on digital core vcc and input plan ivcc 38-41 % of total i cct i v ccp d + i i v ccp d standby mode current on vcc and ivcc pd pin driven low 1 dvi clock stopped > 97 % of total i pd note 1. f o r i 2 c mode: bit pd= 0 .
sii 1 160 panellink t r ansmitter dat a sheet 23 sii -ds-0126-b decoupling capacitors designers should include decoupling and byp a ss cap a citors at each power pin in the layout. these are shown schematically in figure 15. place these component s as cl ose as possible to the panellink device pins, and avoid routing through vias if possible, as shown in figure 14, wh ich is represent ative of the various types of power pins on the transmitter . c1 vc c fer r ite via to g n d vcc gnd c2 c3 l1 figure 14. decoupling and by p ass cap acitor placement vccpin c1 c2 l1 c3 vcc figure 15. decoupling and by p ass schematic the values shown in t able 10 are recommendations that should be adjusted according to the noise characteristics of the specific board- level design. pins in one group (suc h as ivcc) may share c2, l1, and c3, each pin having c1 placed as close to the pin as po ssible. pgnd1 and pgnd2 should be tied individually to ground. t a ble 10. recommended component s for by p ass and decoupling circuit s c1 c2 c3 l1 100 ? 300 pf 2.2 ? 10 uf 10 uf 200+ ?
sii 1 160 panellink t r ansmitter dat a sheet sii -ds-0126-b 24 series damping resistors on outputs series resistors are of ten ef fective in lowering dat a-rela ted emissions and reducing reflections. series resistors with a value close to the impedance of the board traces ar e generally most ef fective in reducing reflections from the input s of the transmitter . if used, resistors should be placed close to the output pins of the vga source or graphics chip, as shown in figure 16. d i e[0. .23 ]/ d i o [ 0 ..2 3] vga figure 16. series input damping resistors for driv ing source source termination resistors on differential outputs source termination, consisting of a 300 ? resistor and a 0.1 f cap a citor , may be used on the dif f erential output s of the sii 1 160 to improve signal swings. see figure 17 for an illu stration. repeat the circuit for each of the four dif f erential output p a irs: tx0 + , tx1 + , tx2 + , txc + . note that the specific value for the source termi nation resistor and cap a citor will depend on the pcb layout and construction. dif f erent values may be needed to create optimum dvi-compliant output waveforms from the trans mitter . 30 0 oh m 0. 1 u f tx0 + tx 0- 30 0 oh m 0.1 u f tx1 + tx2- 30 0 oh m 0.1 u f tx3 + tx3- 30 0 oh m 0.1 u f tx c + tx c- figure 17. differential output source t e rminations source termination suppresses signal reflection to prevent non-dvi compliant receivers from erroneously sampling the tmds signals at high frequencies (beyond 135m hz). the imp a ct on dvi compliant receivers is minimal. therefore silicon image recommends s ource termination for most applications. note that the cap a citor is required to meet dvi idle mode dc of fset requirement s and must not be omitted. note also that the signal suppression requires the r ext _sw i ng value to be changed. power consumption will be slightly hi gher when using source termination.
sii 1 160 panellink t r ansmitter dat a sheet 25 sii -ds-0126-b r c d e t a i l of s our c e t e r m inat ion ( m agni fi ed) r a nd c 060 3 com ponent s instal led. figure 18. source t e rmination lay out illustration the layout in figure 18 has been developed to minimize trace stubs on the dif f erential tmds lines, while providing p ads for the source termination component s (lef t-hand magnified view). source termination component s should be placed close to the transmitter pins. the resi stor and cap a citor are shown inst alled on the p ads provided (right-hand magnified view). differential trace routing the routing for the sii 1 160 chip is relatively simple since no spiral skew compensation is needed. however , a few small precautions are required to achi eve the full performance and reliability of dvi . the t r ansmitter can be placed fairly far from the output connector , but care should be t a ken to route each dif f erential signal p a ir together and achieve impedance of 100 ? between the dif f erential signal p a ir . however , note that the longer the dif f erential traces are betw een the transmitter and the output connector , the higher the chance that external signal noise will couple ont o the low-volt age signals and af fect image quality . do not split or have asymmetric trac e routing between the dif f erential signal p a ir . v i as are very inductive and can cause phase delay problems if applied unevenly within a dif f erential p a ir . v i as should be minimized or avoided if possible by placing all dif f erential tr aces on the top layer of the pcb. figure 19 illustrates an incorrect routing of the dif f erential signal from the sii 1 160 to the dvi connector . figure 20 illustrates the correct method to rout e the dif f erential signal from the sii 1 160 to the dvi connector . figure 21 illustrates recommended routing for dif f erential traces at the dvi connector .
sii 1 160 panellink t r ansmitter dat a sheet sii -ds-0126-b 26 tx figure 19. example of incorrect differential signal routing tx figure 20. example of correct differential signal routing txc - txc + tx0 - tx0 + tx1 - tx1 + tx2 - tx2 + 1 8 9 16 17 24 figure 21. differential t r ace routing to dvi connector (t op side v i ew )
sii 1 160 panellink t r ansmitter dat a sheet 27 sii -ds-0126-b in addition to following the trace routing recommendations, length dif f erences between intr a-p a ir traces listed in column 2 of t able 1 1 and inter-p air traces listed in colu mn 3 of t able 1 1 , should be controlled to minimize dvi skew . s p acing between inter-p air dvi traces should be observed to reduce trace-to-trace couplings. for example, having wider gap s between inter-p air dvi traces will minimi ze noise coupling. it is also strongly advised that ground not be placed adjacent to the dvi traces on the same layer . t able 1 1 list s the recommended limit s for the p a rameters listed above. t a ble 1 1 . routing guidelines for dvi t r aces parameter intra - pa ir (l en g t h o f each trace w i thin a pa ir) inte r-pa ir (l en g t h o f each p a i r co mp ared to o t h e r p a i r s) re c o m m e nde d i n ter?p a i r t r ace sep a rati o n based on 2 la y e r boa r d re c o m m e nde d inte r? p a i r t r ace sep a rati o n based o n 4 l a y e r board max + 0.75 inch + 3 inch min 2x trace w i dth 2x trace w i dth
sii 1 160 panellink t r ansmitter dat a sheet sii -ds-0126-b 28 package dimensions package 100-pin tqfp package dimensions and marking s pecification s i i 1160ctu l l l lll .lll l yyww tt tt tt m d evi c e # lo t # da te code trace c o d e tmds? e1 f1 d1 g1 a2 a1 l1 c e b jedec packag e co d e ms-026-a e d ty p m a x a t h i c k n e s s 1 . 2 0 a1 s t a n d - o f f 0 . 1 5 a2 body thickness 1.00 1.05 d1 body size 14.00 e1 body size 14.00 f1 f o o t p r i n t 1 6 . 0 0 g1 f o o t p r i n t 1 6 . 0 0 l1 lead length 1.00 b lead width 0.20 c lead thickness 0.20 e lead pitch 0.50 dimensions in millimeters. overall thickness a= a1+ a 2. package: sii 1160ctu l e g e n d d e s c r i p t i o n l l l l l l . l l l l l o t n u m b e r y y y ear of mfr ww week of mfr t t t t t t t r a c e c o d e m m a t u r i t y c o d e =0: engineering samples =1: pre-production >1: production figure 22. 100-pin tqfp package dimensions (jedec code ms-026-aed) ordering information s t andard part number: sii 1 160ctu (?u? indicates universal p a ckage usable in both st andard and lead-free environment s)
sii 1 160 panellink t r ansmitter dat a sheet 29 sii -ds-0126-b ? 2005 silicon image. inc. sii - ds-0126-b silicon image, inc. t e l: (408) 616-4000 1060 e. arques a v enue fax: (408) 830-9530 sunnyvale, ca 94085 e-mail: salessupport@siimage.com usa w eb: www .siliconimage.com

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